[LLVMdev] AVX spill alignment

[Jakob Stoklund Olesen]

On Aug 25, 2011, at 4:17 PM, Cameron McInally wrote:

> Hey guys,
> 
> Are spills/reloads of AVX registers using aligned stores/loads?

Yes.

> I can't
> seem to find the code that aligns the stack slots to 32-bytes. Could
> someone point me in the right direction?

The register class has 256-bit spill alignment:

def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
                          256, (sequence "YMM%u", 0, 15)> {
  let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)];
}

/jakob