[LLVMdev] Itineraries in the powerpc backend

[Hal Finkel]

Carter,

When I made the commit, yes. Now, no. The PPC scheduling code was
disabled b/c it did not support bottom-up scheduling (top-down
scheduling is now gone). The lack of support for bottom-up scheduling
had nothing to do with the itineraries, but rather the lack of the
necessary functions for register-pressure information. I intend to add
these in the next week or so, and then things should start to work
sensibly in trunk again.

 -Hal

On Sat, 2011-10-29 at 15:49 +1100, Carter Cheng wrote:
> I hope you don't mind if do have a follow up question- is code in
> place in the code generation supporting "proper" scheduling via the
> processor itineraries in LLVM? 
> 
> 
> 
> 
> On Fri, Oct 28, 2011 at 8:47 PM, Carter Cheng <cartercheng at gmail.com>
> wrote:
>         Thanks Hal. 
>         
>         
>         On Fri, Oct 28, 2011 at 2:19 AM, Hal Finkel <hfinkel at anl.gov>
>         wrote:
>                 Carter,
>                 
>                 In my opinion (and I was the one who committed the
>                 changes in question),
>                 it depends on the hardware. The pipeline descriptions
>                 are for the PPC
>                 440, which is an embedded PPC chip use in a variety of
>                 places. As such,
>                 it is a fairly specific target, and using
>                 pipeline-hazard-based
>                 scheduling for specific embedded targets is not
>                 uncommon. The backends
>                 for ARM and MBlaze have similar pipeline information
>                 for use by their
>                 schedulers.
>                 
>                  -Hal
>                 
>                 
>                 On Thu, 2011-10-27 at 13:28 -0700, Carter Cheng wrote:
>                 > Hello,
>                 >
>                 > I was looking over some of the Target commits. I did
>                 notice some
>                 > detailed pipeline descriptions in the ppc backends.
>                 I havent noticed
>                 > anything in the literature describing this
>                 technique. Is this a
>                 > standard approach for mapping SSA to hardware?
>                 >
>                 > Thanks in advance,
>                 >
>                 > Carter.
>                 
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>                 
>                 --
>                 Hal Finkel
>                 Postdoctoral Appointee
>                 Leadership Computing Facility
>                 Argonne National Laboratory
>                 
>         
>         
> 
> 

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory