[LLVMdev] Bottom-Up Scheduling?

[Hal Finkel]

Is there documentation somewhere for the bottom-up scheduling? I'm
trying to figure out what changes are necessary in order to support it
in the PPC backend.

Thanks in advance,
Hal

On Thu, 2011-10-20 at 10:21 -0700, Evan Cheng wrote:
> 
> On Oct 19, 2011, at 7:29 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> 
> > Evan,
> > 
> > Thanks for the heads up! Is there a current target that implements the
> > scheduling as it will be? And does the bottom-up scheduling also account
> 
> ARM is a good model. 

What part of ARM's implementation is associated with the bottom-up
scheduling? I am confused because it looks like it is essentially using
the same kind of ScoreboardHazardRecognizer that was commented out of
the PPC 440 code.

Thanks in advance,
Hal

> 
> > for pipeline-conflict hazards?
> 
> Yes, definitely. And it should be doing a much better job of it. 
> 
> Evan
> 
> > 
> > -Hal
> > 
> > On Wed, 2011-10-19 at 16:45 -0700, Evan Cheng wrote:
> >> Hi Hal,
> >> 
> >> Heads up. We'll soon abolish top-down pre-register allocation scheduler and force every target to bottom up scheduling. The problem is tt list scheduler does not handle physical register dependency at all but it is something that's required for some upcoming legalizer change.
> >> 
> >> If you are interested in PPC, you might want to look into switching its scheduler now. The bottom up register pressure aware scheduler should work quite well for PPC.
> >> 
> >> Thanks,
> >> 
> >> Evan
> >> 

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory