[LLVMdev] Are x86/ARM likely to support atomics larger than 2 pointers?

[Jeffrey Yasskin]

There's a discussion over on cfe-commits about how future-proof to
make the C1x/C++11 atomic ABI.
(http://lists.cs.uiuc.edu/pipermail/cfe-commits/Week-of-Mon-20111010/047647.html)

One argument is that, because C ABI changes are painful, and
processors may introduce larger atomic operations in the future, we
should try to design the atomics implementation in such a way that it
can take advantage of future instruction sets without needing an ABI
change.

The other argument (apologies if I misstate this) is that atomics
larger than 2 pointers aren't useful, so we shouldn't make anything
more expensive than today's implementation needs, just to support
hypothetical instructions that processors may never implement.


If any of the processor designers on this list want to chime in, this
would be a good time to do so, so the wrong decision doesn't get
written in stone until the next ABI change.


Thanks,
Jeffrey