[LLVMdev] Enhancing TableGen

[David A. Greene]

Che-Liang Chiou <clchiou at gmail.com> writes:

> I understand if you don't want an extra layer of abstraction (which
> adds extra looking-ups to someone reading td files), but I think we
> can have for-loop inside a multiclass without abstractions.

Yeah, I agree.  Putting things directly in the multiclass is better than
separating them out into different classes.  But we would need for loop
support to do it.

> --------------------
> multiclass sse_binop<opcode> {
>  for type = [f32, f64, v4f32, v2f64]
>      regclass = [FP32, FP64, VR128, VR128]
>      suffix = [ss, sd, ps, pd] {
>
>    def !toupper(suffix)#rr : Instr<

Note that I don't necessarily like the above line.  It does obscure the
naming.  I think we can come up with something better.  I was presenting
this as an example of what's possible, not as a prescription for how it
should be done.

                                  -Dave