[LLVMdev] Enhancing TableGen

[Jakob Stoklund Olesen]

On Oct 6, 2011, at 7:59 AM, David A. Greene wrote:

> For example, I want to be able to do this:
> 
> defm MOVH :
>  vs1x_fps_binary_vv_node_rmonly<
>    0x16, "movh", undef, 0,
>           // rr
>           [(undef)],
>           // rm
>           [(set DSTREGCLASS:$dst, 
>                 (DSTTYPE (movlhps SRCREGCLASS:$src1,
>                                 (DSTTYPE (bitconvert
>                                             (v2f64 (scalar_to_vector
>                                                       (loadf64 addr:$src2))))))))],
>           // rr Pat
>           [],
>           // rm Pat
>           [[(DSTTYPE (movlhps SRCREGCLASS:$src1, (load addr:$src2))),
>             (MNEMONIC SRCREGCLASS:$src1, addr:$src2)],
>            [(INTDSTTYPE (movlhps SRCREGCLASS:$src1, (load addr:$src2))),
>             (MNEMONIC SRCREGCLASS:$src1, addr:$src2)]]>;

This kind of thing is very hard to read and understand.

ISAs don't change a lot, and .td files are read lot more than they are written.  I actually think it is preferable to leave some redundancy in the .td files, it makes it much easier to find things.

It is already tedious to expand multiclasses in your head when you are looking for the properties of a specific instruction.

/jakob