[LLVMdev] LLVM and VHDL simulation

[Baggett Jonas]

Hi,

I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process.
To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis is not a list of assembly instructions but a description of a circuit with logical gates. This description is then translated to hardware (which is often done in practice by programming a FPGA).
In consequence, after being synthetised on hardware, not all the VHDL instructions are meant to be executed serially like it is for assembly instructions but they could also be concurrent.
VHDL code could also be simulated by a simulator in which case the concurrent instructions are of course executed serially because the VHDL code is compiled in this case to assembly instructions.
I have no experience with LLVM, but it seems to me that if a VHDL simulator use LLVM for its middleend and backend, it would be hard (if not impossible) to exploit the concurrency of the concerned instructions to do further optimizations.
I find that the author of GHDL (a free VHDL compiler and simulator that is probably the most mature among the free ones) said once to be interested of modifying GHDL to compile to LLVM (see http://www.ruby-forum.com/topic/155103), but now it doesn't seems that anything concrete was made for this project in this area.

Greetings,
Jonas