[LLVMdev] Alternate instruction sequences

[cafxx]

On Thu, 10 Nov 2011 10:17:09 +0100, cafxx wrote:
> On Wed, 09 Nov 2011 09:27:30 -0800, Devang Patel wrote:
>> On Nov 9, 2011, at 12:52 AM, cafxx wrote:
>>
>>> I was wondering, is there any way to express in the IR that an
>>> instruction/instruction sequence/basic
>>> block/region/function/module/whatever is an alternate version of
>>> another?
>>
>> There is not a way to represent --- instruction I1 is an alternative
>> for instruction I2 --- in LLVM IR.
>
> Could there be any interest in this functionality? Do you think 
> bending
> the meaning of existing constructs like
> select i1 undef, <ty> <val0>, <ty> <val1>
> (for instructions) or
> switch i1 undef, label <bb0>, i1 1, label <bb1>
> (for basic blocks) could be feasible/acceptable?

I forgot, the above instructions should be (optionally) marked with 
metadata so that alternates-aware passes can recognize them, e.g.
select i1 undef, <ty> <val0>, <ty> <val1>, !alternates
switch i1 undef, label <bb0>, i1 1, label <bb1>, !alternates