[LLVMdev] predicates and conditional execution

[Evan Cheng]

It's important to point out the current predication support is very limited. For example, the register allocator and instruction schedulers (and most of MI passes) are not predication aware. Also, only ARM uses the if-converter and it's done after register allocation.

There is quite a bit of infrastructure missing to make LLVM a fully predication aware compiler that's appropriate for an arch like IA64.

Evan

On May 24, 2011, at 8:55 AM, Jim Grosbach wrote:

> 
> On May 24, 2011, at 12:02 AM, roy rosen wrote:
> 
>> Hi,
>> 
>> I was wondering if LLVM supports predicates and conditional execution.
>> Something like we have in IA64.
>> There is a register class of predicates and then every instruction may
>> be predicated by a register from this class.
>> For example:
>> 
>> cmp_less p, x, y // p is a predicate which gets the result of x < y
>> p add x, x, 2 // if p then do the add instruction
>> 
>> Is there support in LLVM to something like that?
>> Which architecture can show a good example for the implementation of that?
> 
> 
> Hi Roy,
> 
> LLVM has support for predication. You may want to look at the ARM backend. It has predication for most instructions, and the compiler tries hard to make effective use of the feature. In the target independent code, you'll also want to examine the IfConversion pass, which does most of the heavy lifting for actually making the transformations between explicit CFG and predicated instructions.
> 
> -Jim
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