[LLVMdev] Possible missed optimization?

[Jakob Stoklund Olesen]

On Mar 26, 2011, at 1:04 PM, Borja Ferrer wrote:

> Hello Jakob, thanks for the reply. The three regclasses involved here are all subsets from each other and aren't disjoint. These are the basic descriptions of the regclasses involved to show what i mean:
> 
> DREGS: R31R30, R29R28 down to R1R0         (16 regs)
> DLDREGS: R31R30, R29R28 down to R17R16  (8 regs)
> PTRREGS: R31R30, R29R28, R27R26             (3 regs)
> 
> All classes intersect each other giving as a result the smaller class: DREGSxDLDREGS=DLDREGS / DLDREGSxPTRREGS=PTRREGS, etc. That's why i think the coalescer should work since the regclasses overlap completely.

Cross class coalescing also has some heuristics to prevent it from creating very small register classes. It is possible that it doesn't want to use PTRREGS because it only has 3 registers.

You can look at the output of -debug-only=regcoalescing to see what is going on.

/jakob

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