[LLVMdev] Noob Backend Orientation

[Alexander Jordan]

Hey Brian,

On 03/15/2011 03:02 PM, Brian Mokrzycki wrote:
> 	Second, related to the previous, if I were to only maintain the assembly/ISA description in LLVM, can LLVM produce a simulator to execute target specific machine code binaries?  I realize that you can, in theory, translate the ll assembly to the host machines processor architecture as a pseudo-simulation, but this doesn't give you hardware specific information about your real target machine, such as what is stored in register r6 at breakpoint 10.

As already pointed out, LLVM's target description is not sufficient 
here. You might be interested in generating simulators (and other tools) 
from structural architecture descriptions [1], which is a research topic 
of a colleague of mine [2] and also makes use of LLVM.

> 	Lastly,  the DSP processor is a VLIW/EPIC machine.  I assume that this fact is going to produce a few hiccups when creating the LLVM backend, just like it did when I was doing the binutils port.  Any words of wisdom would be very welcome on this front.

Getting your initial VLIW backend off the ground should not be too hard. 
It will be unoptimized and probably only limited to a subset of the ISA, 
but on the other hand LLVM does a good job compensating for features 
your architecture does not support. I think a good example is the 
experimental C64X backend mentioned here [3].

Once you are looking into performance, especially wrt. to scheduling 
(bundling) issues, things get more complicated. I have found the common 
target machine and schedulers too restrictive and had to work around the 
Codegen vs. Target separation in LLVM a bit. Feel free to dig through my 
git repository [4].

cheers,
alex

[1] 
http://www.complang.tuwien.ac.at/cd/brandner/papers/rapido09-brandner.pdf
[2] http://perso.ens-lyon.fr/florian.brandner/
[3] http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-August/033821.html
[4] http://www.complang.tuwien.ac.at/ajordan/llvm-tic64x.git