[LLVMdev] Vector select/compare support in LLVM

[Duncan Sands]

Hi Nadav,

> The problem with the sparse representation is that it is word-width dependent. For 32-bit data-types, the mask is the 32nd bit, while fore 64bit types the mask is the 64th bit.
>
> How would you legalize the mask for the following code ?
>
> %mask = cmp nge<4 x float>  %A, %B                   ;<4 x i1>
> %val  = select<4 x i1>% mask,<4 x double>  %X, %Y ;<4 x double>

I would expect this to become

%mask = cmp nge<4 x float> %A, %B with result type <4 x i32>
%mask_lo = extract elements 0, 1 from %mask, result type <2 x i64>
%mask_hi = extract elements 2, 3 from %mask, result type <2 x i64>
%val_lo = select <2 x i64> %mask_lo, <2 x double> %X_lo, %Y_lo
%val_hi = select <2 x i64> %mask_hi, <2 x double> %X_hi, %Y_hi

>
> Moreover, in some cases the generator of the mask and the consumer of the mask are in different basic blocks. The legalizer works on one basic block at a time. This makes it impossible for the legalizer to find the 'native' representation.

I don't understand what you are saying here.

Ciao, Duncan.

>
> I wrote down some of the comments which were made in this email thread:
>
> http://wiki.llvm.org/Vector_select
>
>
> Cheers,
> Nadav
>
>
> -----Original Message-----
> From: David A. Greene [mailto:greened at obbligato.org]
> Sent: Thursday, March 10, 2011 18:57
> To: Rotem, Nadav
> Cc: David A. Greene; llvmdev at cs.uiuc.edu
> Subject: Re: [LLVMdev] Vector select/compare support in LLVM
>
> "Rotem, Nadav"<nadav.rotem at intel.com>  writes:
>
>> One of the arguments for packing masks is that it reduces
>> vector-registers pressure.  Auto-vectorizing compilers maintain
>> multiple masks for different execution paths (for each loop nesting,
>> etc).  Saving masks in xmm registers may result in vector-register
>> pressure which will cause spilling of these registers.  I agree with
>> you that GP registers are also a precious resource.
>
> GPRs are more precious than vector registers in my experience.  Spilling
> a vector register isn't that painful.  Spilling a GPR holding an address
> is disastrous.
>
>> In my private branch, I added the [v4i1 .. v64i1] types. I also
>> implemented a new type of target lowering: "PACK". This lowering packs
>
> Is PACK in the X86 namespace?  It seems a pretty target-specific thing.
>
>> I also plan to experiment with promoting<4 x i1>  to<4 x i32>.  At
>> this point I can't really say what needs to be done.  Implementing
>> this kind of promotion also requires adding legalization support for
>> strange vector types such as<4 x i65>.
>
> How often do we see something like that?  Baby steps, baby steps...  :)
>
>                                  -Dave
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