[LLVMdev] code generation for ARM

[Griffin Wright]

I believe you indeed need to specify some ARM-related things when buliding
LLVM and LLVM-gcc (if you are compiling it from source). Below are the
configurations I used, I believe. I may have tweaked them a bit, but this
was the general idea: 

Configure llvm:
 ../llvm-2.9/configure --target=arm-none-linux-gnueabi
--prefix=/home/grwright1/Research/llvm/llvm-install
--with-llvmgccdir=/home/grwright1/Research/llvm/llvm-gcc --disable-multilib
--disable-bootstrap --disable-optimized --enable-shared --enable-assertions
--enable-languages=c,c++

Configure llvm-gcc:
 ../llvm-gcc-4.2-2.9.source/configure
--target=arm-none-linux-gnueabi
--program-prefix=llvm-arm-
--prefix=/home/grwright1/Research/llvm/llvm-gcc/install
-with-sysroot=/home/grwright1/Research/llvm/arm-2010q1/arm-none-linux-gnueabi/libc
--with-gnu-ld=/home/grwright1/Research/llvm/arm-2010q1/bin/arm-none-linux-gnueabi-ld
--with-gnu-as=/home/grwright1/Research/llvm/arm-2010q1/bin/arm-none-linux-gnueabi-as
--with-gnu-ar=/home/grwright1/Research/llvm/arm-2010q1/bin/arm-none-linux-gnueabi-ar
--enable-llvm=/home/grwright1/Research/llvm/llvm-obj --disable-optimized
--disable-multilib --disable-bootstrap --disable-shared --enable-checking
--enable-languages=c,c++ 

-Griffin 

On Tue, 14 Jun 2011 13:53:13 -0400, D S Khudia  wrote: Thanks for your
reply.

 I have a normal (../configure --enable-profiling --disable-optimized
--enable-assertions) llvm debug+profile+assert build. 
   I am generating llvm-bitcode using following commands.  llvm-gcc
-DLINUX_i386 -DSPEC_CPU2000 -O3 -emit-llvm 186.crafty/src/valid.c -c
-o
186.crafty/src/valid.bc  ---  llvm-link 186.crafty/src/*.bc -o
186.crafty/186.crafty.rel.bc  and finally:  llc -march=arm
186.crafty/186.crafty.rel.bc -o 186.crafty/186.crafty.m5arm.s  And there is
not inline assembly in my C code.  Should I somehow specify arm related
options to llvm while building llvm?  Thanks Daya  On Tue, Jun 14, 2011 at
1:34 PM, Anton Korobeynikov  wrote:
 Hello

 > Command => llc -march=arm 186.crafty/186.crafty.rel.bc -o
 > 186.crafty/186.crafty.m5arm.s
 > Error => LLVM ERROR: Couldn't allocate output reg for constraint '{cx}'!
 >
 > Have anyone seen this before? It seems you're feeding x86-specific LLVM
IR to arm backend. Please
 don't do that.

 --
 With best regards, Anton Korobeynikov
 Faculty of Mathematics and Mechanics, Saint Petersburg State University

 

Links:
------
[1] mailto:anton at korobeynikov.info
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