[LLVMdev] Possible CellSPU Bug?

[Kalle Raiskila]

David Greene wrote:

> class XSHWVecInst<ValueType in_vectype, ValueType out_vectype>:

>   def v4i32: XSHWVecInst<v4i32, v8i16>;

> Is this pattern as intended, or did I find a real problem?

Looks like a bug to me. xshw (extend signed half-word(16bits) to
word(32bits)) takes a v8i16 and produces a v4i32. This has likely gone
unnoticed as there is only one type of vector register class (i.e.
VECREG) that is used for all vectors.

Nice catch :) Are there more of these?


kalle

-- 
"Modern computing machines are very complex objects"
                      -von Neumann introducing the NORC, 1954