[LLVMdev] Question about porting LLVM - code selection without assembler feature

[David A. Greene]

Lu Mitnick <king19880326 at gmail.com> writes:

> Hello David,
>
> Thanks for your example. Is that means that DAG pattern is consist of
> LLVM IR instruction?? I met an example  [(set CPURegs:$dst, (OpNode
> CPURegs:$b, CPURegs:$c))] of MipsInstrInfo.td, but I can't find
> correspond LLVM IR instruction of "set" in "LLVM Language Reference
> Manual". Is that correspond to $dst = op $b, $c?? Would you mind to
> tell me whether there is a reference of all possible element of DAG??

Ah.  No, it's not LLVM IR.  It's SelectionDAG IR.  The operations are
defined in include/llvm/CodeGen/ISDOpcodes.h.  Each target also has its
own set of operations.  For example, the x86 target has operators for
x86-ish things like odd shuffles and so forth.  Since you're writing
your own target, you may end up defining some.  If your target is simple
enough, you won't.

The actual nodes used in patterns are defined in
include/llvm/Target/TargetSelectionDAG.td.  You'll see an almost 1:1
correspondence between ISDOpcodes.h and TargetSelectionDAG.td.

In addition, there are some special operators that TableGen recognizes.
"set" is one of them.  It's pure syntactic sugar.  TableGen just throws
it away.  It's only there to make patterns look prettier.

To find these special operators, you can look in TargetSelectionDAG.td
for the stuff that doesn't have anything matching in ISDOpcodes.h.  To
know what they do, you have to read the TableGen source, currently.  :(

TableGen is confusing stuff, but really powerful once you grok it.

                      -Dave