[LLVMdev] How to avoid register reuse in machine instructions?

[Andrew Clinton]

Is there a way to force the register allocator to avoid reusing an 
operand register for a definition?  For example, the following machine 
instruction reuses a register for the first operand and definition:

%uI7<def> = eq at III %uI7<kill>, %uI4

I'd like:

%uI8<def> = eq at III %uI7<kill>, %uI4

I'm guessing that the right way to do this would be to kill the operand 
registers after the given machine instruction rather than before it, but 
I don't see a way to mark it this way.

Andrew