[LLVMdev] X86 LowerVECTOR_SHUFFLE Question

[Bruno Cardoso Lopes]

> In the experience I just had, it is quite error-prone to have multiple
> tblgen patterns to match these things.  The way things were before,
> there was a clean separation between checking/enforcing node legality
> and doing the final code selection, with isel being automatic through
> tblgen.  That was nice.  The current setup mixes the two and seems to
> result in more code in the form of additional tblgen patterns.  We also
> lose the ability to do shuffle peeps or any other such things unless we
> teach the code about every type of special target node.
>
> It really doesn't seem worth it to me.

In the way it was done before, every shuffle that we tried to match
had to be checked twice (masks used to be checked during legalization
and during isel by the tblgen patterns), this is done only once now
(during legalization). Although we still match the node itself through
tblgen patterns, the tablegen patterns are a lot more clear now, and
we were able to remove lots of confusing code. The code used to be
*very* fragile, during legalization there was no explicit rule or
comments of what and when stuff needed to be matched (and changing a
single rule would generate a code that would fail to match tblgen
patterns later), all the logic was getting really hard to understand.
The long term plan is: generate all target specific nodes during
legalization, and once all logic is clear, we can go for more fancy
stuff like having per-processor family shuffle tables
describing the more profitable shuffles for a specific mask, and so
on. The work stopped because of this bug:
http://llvm.org/bugs/show_bug.cgi?id=8156, but IMHO the implementation
of x86 shuffle matching is a lot more clear now then they used to be
in the past.

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc