[LLVMdev] Stop MachineCSE on certain instructions

[Jim Grosbach]

Ah, OK. I think I understand much better now. Thanks! You shouldn't need bundles for that sort of thing. A custom lowering or a fancy pattern should be sufficient, depending on the details of how your target is defined.

For patterns, looks at the various targets use of the Pat<>, Pattern<>, ComplexPattern<> and related classes in the .td files.

For examples of custom lowerings, have a look at how other targets handle any operations marked in <TargetName>ISelLowering.cpp as "Custom" operation actions.

-Jim

On Dec 20, 2011, at 6:57 PM, girish gulawani wrote:

> 
> Hi, Jim.
> In my case the target (Tilera) doesn't have a full 32-bit mult operation and to do so it has to accumulate results from three 16-bit mults, by retaining operands and the result across in the same registers. However the ISel DAG thinks its a CSE case. Please note this is not a MAdd/MSub triad.
> 
> How could I do this by defining such a sequence or the pattern in the .def file itself for the ISD::MUL?
> Thanks.
> Girish.
> 
> From: Jim Grosbach <grosbach at apple.com>
> To: girish gulawani <girishvg at yahoo.com> 
> Cc: Johannes Birgmeier <e0902998 at student.tuwien.ac.at>; LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> 
> Sent: Wednesday, 21 December 2011 12:41 AM
> Subject: Re: [LLVMdev] Stop MachineCSE on certain instructions
> 
> Hi Girish,
> 
> Sorry, but I'm afraid I don't understand your question. Can you elaborate a bit?
> 
> -Jim
> 
> On Dec 19, 2011, at 9:12 PM, girish gulawani wrote:
> 
> > 
> > Hello Jim.
> > Just out of curiosity, won't such mechanism work via the patterns from instructions defs?
> > 
> > Thanks.
> > Girish.
> > 
> > From: Jim Grosbach <grosbach at apple.com>
> > To: Johannes Birgmeier <e0902998 at student.tuwien.ac.at> 
> > Cc: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> 
> > Sent: Monday, 19 December 2011 10:33 PM
> > Subject: Re: [LLVMdev] Stop MachineCSE on certain instructions
> > 
> > Hi Johannes,
> > 
> > You may be interested in the (very) recently added explicit instruction bundle support. For an example of their usage, have a look at the ARM backend's IT-block (Thumb2 predication support) pass, which uses them to tie instructions together.
> > 
> > -Jim
> > 
> > On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote:
> > 
> > > Hello,
> > > 
> > > I'm writing for a backend and have a complicated instruction bundle (3 
> > > instructions) that has to be executed like a single block (meaning: if 
> > > the first instruction is executed, all three have to be executed to 
> > > obtain the result, though not necessarily without other instructions in 
> > > between). Unfortunately, MachineCSE gets in the way sometimes and rips 
> > > it apart.
> > > 
> > > Is there a way to stop CSE from doing its thing (common subexpression 
> > > elimination) for certain instructions?
> > > 
> > > I've already tried glueing (gluing?) them together, but that doesn't 
> > > seem to make a difference.
> > > 
> > > Regards,
> > > Johannes Birgmeier
> > > _______________________________________________
> > > LLVM Developers mailing list
> > > LLVMdev at cs.uiuc.edu        http://llvm.cs.uiuc.edu
> > > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
> > 
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> > 
> > 
> 
> 
> 

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