[LLVMdev] [LLVM, llc] TypeLegalization, DAGCombining, vectors loading

Stepan Dyatkovskiy STPWORLD at narod.ru
Tue Dec 13 23:59:55 PST 2011

> The further you go, either in the conceptual distance
> between code and target machine, or in diversity of target
> machines, the worse the problem gets.
Yes. Very SelectionDAG seems very complex for me. I spend all previous week to learn it, but only now I'm begin to understand how all its parts cooperates together.

> Also, all of the proposed solutions for fixing exotic
> vector types have substantial downsides.

> So in addition to asking "why doesn't <2 x i5> work?", it's
> also useful to ask "who is producing <2 x i5> values, and
> what am I expecting to get out of letting them do that?"
2 x i5 ... Probably is not used anywhere. May be in 29 bit CPUs... But what about N x i1 or N x i4? Since llvm assumes byte addressing there is a reason to extend this kind of vectors to N x i8. This is a complex problem though. Probably I missed something. But I have some draft patches that fixes load+store problem for arm and for X86 rounding the size of vector element.


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