[LLVMdev] [llvm-commits] Vectors of Pointers and Vector-GEP
David A. Greene
greened at obbligato.org
Thu Dec 1 09:15:05 PST 2011
"Rotem, Nadav" <nadav.rotem at intel.com> writes:
> The scenario you described is probably the most important/common
> case. Supporting GEPs with a scalar base pointer and multiple indices
> can indeed assist IR-level optimizations in detecting these patterns
> and replace them with intrinsics. But even without a single scalar
> base pointers, optimizations can detect that the base pointer is
> broadcasted from a scalar.
I just wrote an extensive reply that covers this. I think we do want a
scalar base GEP to make isel easier and the IR more target-independent.
We should also consider a strided GEP (also covered in my reply) for the
> Having said that, I am still not sure how to add codegen support for
> AVX2 scatter/gather of base + 32bit-indices. The problem is that the
> GEP would return a vector of pointers, which need to be reversed back
> to the 'base+index' form. I think that replacing the GEP/LOAD sequence
> with an intrinsic if probably the best choice.
In the same reply I mentioned various index generation instructions like
cidx. This allows you to retain the index set separate from the final
addresses. You'd then match load (gep(base, <0>, index set)) as the
gather operation in isel, similar to how memops are done for X86 today
(i.e. manual lowering would put the GEP information in special address
match data structures).
The same can be done without cidx, but you need a more complex
instruction sequence to generate the index set and match that in the
address manual lowering code. This does make the manual address
matching code more complicated.
There are lots of options here but I do think we need something beyond
the simple "all vector" GEP.
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