[LLVMdev] cortex-m{3,4} special registers

[Jim Grosbach]

Hi Kurt,

The assembly parser doesn't (yet) handle these, you're right. Currently, the MRS instruction is split into two variants in the ARMInstrThumb2.td file, t2MRS and t2MRSsys, one for the user mode version reading cpsr and one for the system mode version reading spsr. MSR, by contrast, has a custom parse method for the mask operand since it's a bit more complex than an either/or.

You'll likely want to merge the two MRS variants into one and add an operand for the system register, mapping that to the proper encoding bits in the instruction, and use a custom parse method to map the register names to the appropriate bit values. The current MSR parse method should give a basic idea of how to do that.

Once you have something, post a proposed patch to llvm-commits and we'll have a look and work through any implementation details.

Regards,
-Jim



On Aug 28, 2011, at 1:02 PM, Kurt Lidl wrote:

> I was attempting to compile some code with a recent (r138716)
> version of llvm/clang, targeting a cortex-m4 processor.
> 
> And I get an error like this:
> 
> CC:  sched_garbage.c
> In file included from sched_garbage.c:43:
> In file included from ./os_internal.h:48:
> In file included from /p/nuttx/trunk/nuttx/include/sched.h:47:
> In file included from /p/nuttx/trunk/nuttx/include/nuttx/sched.h:54:
> In file included from /p/nuttx/trunk/nuttx/include/nuttx/irq.h:67:
> In file included from /p/nuttx/trunk/nuttx/include/arch/irq.h:60:
> /p/nuttx/trunk/nuttx/include/arch/armv7-m/irq.h:186:6: error: invalid operand
>      for instruction
>     "\tmrs    %0, primask\n"
>     ^
> <inline asm>:1:14: note: instantiated into assembly here
>                mrs    r5, primask
>                           ^
> 
> This appears to be due to llvm lacking support for the various
> cortex-m{3,4} special registers.  ("primask", "faultmask", etc)
> 
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0491c/ch05s13s01.html
> 
> Can someone tell me how I would go about adding support for these
> special registers?
> 
> -Kurt
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev