[LLVMdev] Register Pressure Computation during Pre-Allocation Scheduling

[Eli Friedman]

On Tue, Aug 16, 2011 at 2:08 AM, Ghassan Shobaki
<ghassan_shobaki at yahoo.com> wrote:
>
> Thank you for the answers, Jakob! That's really informative for someone who
> is still new to LLVM like me. Please see my responses below.
> -Ghassan
>
> ________________________________
> From: Jakob Stoklund Olesen <stoklund at 2pi.dk>
> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com>
> Cc: "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu>
> Sent: Tuesday, August 16, 2011 12:52 AM
> Subject: Re: [LLVMdev] Register Pressure Computation during Pre-Allocation
> Scheduling
>
>
> On Aug 15, 2011, at 1:27 AM, Ghassan Shobaki wrote:
>>This information is only computed immediately before register allocation.
>> Passes that run after scheduling can significantly change the register
>> pressure. In
>> particular MachineCSE and MachineLICM do this.
>
> Ghassan: I know that phase ordering is a non-trivial problem that does not
> have a perfect solution (like most compiler optimization problems!), but I
> wonder why LLVM runs such passes between scheduling and allocation. One
> would expect a register pressure reduction pass to be placed as close as
> possible to the register allocation pass. Ideally, you would like to have an
> integrated algorithm that does allocation and scheduling simultaneously, but
> such an integrated solution is usually not implemented due to its
> complexity. So, my questions are:
> (1) CSE naturally tends to increase reg pressure. Is there any particular
> reason for doing CSE between scheduling and allocation instead of doing it,
> say before scheduling?

There are essentially three relevant phases to code generation here:
adjustments to LLVM IR (which you probably don't care too much about),
instruction selection which translates IR into MachineInstrs, and
transformations on MachineInstrs.  The stuff before and after isel is
reasonably flexible; isel itself is quite rigid.  The CSE and LICM
passes in question are MachineInstr transformations; pre-RA scheduling
is essentially the last phase of instruction selection.

> (3) Does LLVM have command-line options for turning off phases like CSE and
> LICM?

Try passing -help-hidden to llc.

-Eli