[LLVMdev] Register Pressure Computation during Pre-Allocation Scheduling

[Jakob Stoklund Olesen]

On Aug 15, 2011, at 1:27 AM, Ghassan Shobaki wrote:

> One factor that is causing our current register pressure estimate to be off is not being able to properly account for live-in and live-out registers (both virtual and physical). As far as we can tell, LLVM represents live-in regs with CopyFromReg instrs and live-out regs with CopyToReg instrs. However, it looks that in a given basic block, LLVM does not generate CopyToReg instrs for registers that are not defined within that block and does not generate CopyFromReg instsr for regs that are not used within the block. This is causing a problem for us, because a precise register pressure estimate has to take into account all live regs at a given point in the block whether they are defined or used in the block itself or not. Our questions are:
> 
> (1) How can we get information about the registers that are live within a basic block but are not defined within the block? And how can we get that information for regs that are not used in the block?

This information is only computed immediately before register allocation. Passes that run after scheduling can significantly change the register pressure. In particular MachineCSE and MachineLICM do this.

We also run value-based copy coalescing before register allocation. That usually reduces register pressure.

> (2) Can we safely assume that CopyFromReg instrs and CopyToReg instrs are used for the sole purpose of representing live-in and live-our regs? In other words, are there other uses for these?
> If yes, how do we identify the ones that represent live-in and live-out regs.

These DAG nodes are also used to copy to/from physical registers before and after calls.

Virtual registers defined by PHI instructions will also appear as CopyFromReg operands.

> (3) The current physical regsiter limits obtained using 
> TargetRegisterInfo::getRegPressureLimit()
> seem to be too low (for example, 3 integer regs on x86 32-bit mode). Are these good limits to use in our case? If not, how can we get better limits?

These limits are low exactly to make room for the global registers passing through a block without being used. The x86-32 architecture has so few registers that you pretty much always want to schedule for register pressure.

Note that LLVM 3.0 has a new register allocator with live range splitting. That makes it less important to accurately model the register pressure from global live ranges. These ranges are likely to be split and spilled anyway, so the schedule should not necessarily make room for them.

/jakob

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