[LLVMdev] Instructions with register constraints

[Damien Vincent]

 For any instruction, a list of constraints can be specified, like:
let Constraints = "$dst = $lhs" in
...

 I checked the existing backends and I didn't notice any complex
constraints: basically "Constraints" keyword is used to force 1 operand
register to be the same as  another one.
I am wondering if there is any way to express more complicated constraints
like for example:
- if $lhs is either r0,r1,r2,r3 then $dst should also be in the set
{r0,r1,r2,r3}
- if $lhs is either r4,r5,r6,r7 then $dst should also be in the set {r4, r5,
r6, r7}
...

  Thank you !

  Damien
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