[LLVMdev] comparison pattern trouble

[Heikki Kultala]

Our architecture has 1-bit boolean predicate registers.

I've defined comparison


def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;




But then I end up having the following bug:


Code


  %0 = zext i8 %data to i32
  %1 = zext i16 %crc to i32
  %2 = xor i32 %1, %0
  %3 = and i32 %2, 1
  %4 = icmp eq i32 %3, 0


which compares the lowest bits of the 2 variables


ends up being compiled as


        %reg16384<def> = LDWi <fi#-2>, 0; mem:LD4[FixedStack-2] I32Regs:%reg16384
        %reg16385<def> = LDWi <fi#-1>, 0; mem:LD4[FixedStack-1] I32Regs:%reg16385
        %reg16386<def> = COPY %reg16384; I32Regs:%reg16386,16384
        %reg16390<def> = NErrb %reg16384, %reg16385; I1Regs:%reg16390 I32Regs:%reg16384,16385


which just compares ALL BITS of the variables.


Any idea what is causing this and how this could be fixed?