[LLVMdev] Register design decision for backend

[Borja Ferrer]

Hello Jakob,
as mentioned in my previous email i'm unable to work with register pairs and
let LLVM split i16 data into two i8 regs. If you know a way of doing it
without heavy customization for each operation please let me know.

As an alternative i could work only with i8 regs so that LLVM is able to
split types, this the only way i've found so far. Doing this would imply the
following changes:

1) store i16 or wider data in odd:even reg pairs (r5:r4 and not r4:r3),
achieved with a register allocation hint?

2) convert all reg to reg moves that work on register pairs to one 16bit
move. Thus folding two 8bit moves into one 16bit move. I'm a bit uncertain
if this is possible to do by only working with 8 bit regs. I thought that
maybe this could be done with some "Function Pass" before register
allocation? One important thing to notice is that it's not guaranteed that
the 2 moves come in a row, they could come out of order or have other
instructions in between,  thats why i prefer doing it before reg allocation.
Since reg to reg moves are handled in a different way than the rest of
instructions is this manageable?

3) load/store functions only work with register pairs. Here i think it would
have to be handled in the selectionDAG?

Thanks for the help.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100908/342e373b/attachment-0001.html>