[LLVMdev] [Q] x86 peephole deficiency

[Chris Lattner]

On Oct 13, 2010, at 11:22 AM, Gabor Greif wrote:

> Hi Chris,
> 
> I had a look into MachineCSE, but it looks like MBB-oriented.
> The above problem is an inter-block one. Also MCSE seems
> to perform value numbering on virtual/physical registers, which
> does not map very well to status register bits that are implicitly
> defined.
> Any chance to recast this issue as a target-independent
> (but cmp-specific) peephole problem, that just looks into
> predecessor blocks and applies (target-hook-like) subsumption
> checks for 'cmp' instructions?

I think that extending MachineCSE to do a simple dominator tree walk with llvm::ScopedHashTable would make sense.

Status register bits should be handled just like any other physreg.  On x86, this is a def of EFLAGS physreg for example.  On PPC, the condition code register is actually a vreg iirc.

-Chris