[LLVMdev] ARM Intruction Constraint DestReg!=SrcReg patch?

[maarten faddegon]

Hi,

Paul Curtis wrote:
> If you read the Arm Architecture document for ARMv5, it states for MUL:
> 
> "Operand restriction:  Specifying the same register for <Rd> and <Rm> was
> previously described as producing UNPREDICTABLE results. There is no
> restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5
> implementations do not require this restriction either, because high
> performance multipliers read all their operands prior to writing back any
> results."
> 
> Therefore I do not believe you need to worry about this at all. 

However, ARM support wrote:
> The restriction on Rd == Rm was removed in ARMv6, but this was not a
> retrospective change.  That is, for ARMv4T and ARMv5TE the combination is
> still officially unpredictable.
> 
> The comment in the ARM Architecture Reference Manual is intended as a
> helpful note.  However, in some ways it is unhelpful as there is still
> no guarentee that a given implementation will support it.The
> comment has since been removed from the latest edition.
> 
> The advise would be to assume that restriction still applies to ARMv4T or
> ARMv5TE when developing portable code

Thus, if I want to follow this advice, is there a way to force LLVM to 
not output instructions such as "mul r0, r0, r2"? As I believe was the
effect of the Lauro Ramos Venancio's patch.

kind regards,
  Maarten Faddegon