[LLVMdev] subregs in trivial coalescing

[Jakob Stoklund Olesen]

On Nov 18, 2010, at 5:19 AM, Krister Wombell wrote:

> Q1 (a 128-bit physical register) is assigned to %reg16402 which is ok but then RALinScan::attemptTrivialCoalescing thinks it can coalesce r16405 with r16402 giving:
> 
> 92L	Q1:dsub0<def>        = DEF64 %reg16402<imp-def>, QPR:%reg16402
> 116L	Q1:sub0<def>         = COPY Q1:sub1, %reg16405<imp-def>; QPR:%reg16405,16402
> 124L	%reg16413:sub0<def>  = COPY Q1:sub0; QPR:%reg16413,16405
> .... stuff ....
> 468L	%reg16460:sub3<def>  = COPY Q1:sub0<kill>; QPR:%reg16460,16402
> 
> which is wrong: Q1:sub0 (in reg16402) is overwitten at 116 before it's last use at 468.
> 
> Trivial coalescing doesn't have any check for subregs so I'm assuming that something is broke. I've patched things up by rejecting any trivial coalescing attempt where the COPY has a subregister as it's target (none of the tests for arm and x86 hit this case).
> 
> Does that seem right?  Not sure if I've misused subregs or if the input to the RA is incorrect?

It looks like you found a bug.

This code has probably been tested mostly with x86 code where such a sub-register mismatch is not possible.

The trivial coalescing after allocation is a bit fragile, and I think you are right to disable it when the copy destination is a sub-register.

Do you have a patch?

/jakob

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