[LLVMdev] backend question

[Jakob Stoklund Olesen]

On May 26, 2010, at 1:57 AM, Lev Yudalevich wrote:

> Thank you very very much for your answer!
> 
> Am I correct in my understanding that "let Defs = [CPSR]" in the definition of AI1_bin_s_irs multiclass explains the effect of setting conditional codes to the TableGen in ARM's case?

Yes, that tells the instruction selector and scheduler that the CPSR register is clobbered by this instruction.