[LLVMdev] llvm and flushing instruction cache

[Shasank Chavan]

Thanks, and thanks Jeffrey for your response as well.  So I see in Memory.cpp in sys_icache_invalidate() that we only invalidate the cache for powerpc.  Can you point me to any literature that describes how for x86 the processor handles these modifications automatically?  Does this work, by the way, for both AMD and Intel chips? - on Linux and NT?  Thanks.

 

- Shasank

 
> Date: Sat, 6 Mar 2010 23:19:28 -0800
> Subject: Re: [LLVMdev] llvm and flushing instruction cache
> From: eli.friedman at gmail.com
> To: shanko_chavano at hotmail.com
> CC: llvmdev at cs.uiuc.edu
> 
> On Sat, Mar 6, 2010 at 10:34 PM, Shasank Chavan
> <shanko_chavano at hotmail.com> wrote:
> > Hi.  I have a very quick question.  Is the instruction cache flushed by the
> > llvm jit before code in memory is written to or executed?  I'm assuming so,
> > but I can't find where in the source code this is happening.  In particular
> > I searched for clflush, invd, and wbinvd instructions, but couldn't find
> > them.  And if it's not necessary to do this, can you please explain why?
> > (I'm assuming the target platform has a separate L1 i-cache).  Thanks.
> 
> On x86 in particular, explicitly flushing the instruction cache isn't
> necessary; the processor transparently handles modifications to cached
> code.
> 
> -Eli
 		 	   		  
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