[LLVMdev] Scheduling and alias analysis

[Evan Cheng]

On Jul 22, 2010, at 7:42 AM, Amaury Pouly wrote:

> Hello,
> I have recently been working on scheduling for register pressure and ran into the issue of alias analysis when trying to integrate it with LLVM.
> Looking at the code it seems that the pre register allocation scheduling doesn't use alias analysis information. On the contrary, post-RA uses it.
> I'm wondering if there is a good reason for this fact. Indeed, it seems to me that alias analysis would be much more useful before register allocation when the scheduler still has the opportunity to really move the memory related instructions.
> Am I missing something ? Wouldn't it be possible to use alias analysis when building the pre-RA schedule graph ?

I don't consider this a scheduling issue. The real problem is in instruction selection. When sdiel builds the DAG it  doesn't eliminate the "chains" between memory SDNodes which do not alias. This is something we want to do but just haven't gotten to it.

Evan

> 
> Regards
> 
> Amaury Pouly
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