[LLVMdev] SelectionDAG legality: isel creating cycles

[Chris Lattner]

On Feb 22, 2010, at 8:41 AM, David Greene wrote:

> On Monday 22 February 2010 10:31:24 David Greene wrote:
> 
>> The fundamental issue is that the DAG originally looked like this:
>> 
>> MIN
>>  LOAD B
>>    PREFETCH
>>      Chain from LOAD A
>>  LOAD A
> 
> Actually, it looked like this:
> 
> MIN
>  LOAD B
>    Chain from PREFETCH
>      Chain from LOAD A
>    NULL
>  LOAD A
>    Chain from ENTRY
>    Some Addressing
> 
> LOAD B is from NULL because this is a bugpoint-reduced testcase, so that's not 
> an issue.
> 
> Just wanted to clarify in case someone was wondering about this.

I'm currently working in this area.  What pattern is causing the cycle?  Can I get a testcase?

-Chris