[LLVMdev] Original data type after DAG legalization

[Borja Ferrer]

Hello Duncan, first thanks for the reply, as requesterd i'll explain the
situation for why i need this sort of information:

The backend im currently writing targets an 8bit MCU (which i hope it gets
included in LLVM in the future) that requires some special register
constraints. Basically the only legal type is 8bit, so the rest of wider
operations get expanded by the legalizer.
When we reach to the register allocator stage things get a bit more complex
because we need to meet some constraints. The basic rules are:

(here when i say data type i mean the data type before legalization, since
after legalization everything will be 8bits)
1) if the data type is 8bit (it wasn't expanded) it can be allocated in any
phys reg, so there are no contraints.
2) if the data type is 16bit (expanded into two 8 bit regs) it has to be
allocated in a phys register pair, mapping the lo part into an even phys reg
and the hi part into an odd phys reg. In other words, the two allocated
registers must be adjacent and the ordering of the pair must be odd:even. So
for example:
HIGH:LOW
R11:R7 is illegal because regs arent adjacent
R10:R11 is illegal because, although regs are adjacent, the lo part is
mapped into an odd reg which is the opposite of what we want.
R11:R10 is legal, we have adjacent regs and the pair has the order we want,
odd mapping the hi part and even mapping the lo part.
3) wider types follow the same constraints as point 2.

I've accomplished storing 16bit or wider data in register pairs using the
PBQP register allocator, however, to get the right ordering of the pair
(odd:even), if i have two 8bit vitual regs x and y that map a 16 bit value,
i need to know which one is mapped into the lo part and which is one is
mapped to the hi part so the allocator allocates an even reg to the lo part
and an odd to the hi part. Since i dont know a way of getting this sort of
information i'm getting unordered pairs because the allocator thinks that
the cost of an unordered pair is the same as the cost for an ordered pair.
If i knew that for example reg x is the lo part and reg y is the hi part, i
could build the cost matrix for the regalloc according to my constraints,
but because i dont know how to get this info currently i'm only getting
adjacent regs allocated which is only 50% of my constraints.

In gcc you would use HARD_REGNO_MODE_OK(REGNO, MODE),
http://gcc.gnu.org/onlinedocs/gccint/Values-in-Registers.html#index-HARD_005fREGNO_005fMODE_005fOK-3967
in this description you can see it does exactly what im commenting here.

This is basically why i need to get this information, if i'm taking the
wrong way please let me know so i can make this work :)

Thanks for reading this.
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