[LLVMdev] [LLVMDev] Register Allocation and Kill Flags

[Andrew Trick]

I'm sure you found your answer, but I never saw a response on the list. Here's my take.

Kill flags are used in a few places after regalloc (postRA scheduling, register scavenging...) to conservatively estimate liveness. Machine verification is intended to confirm that kill flags match liveness. But machine verification isn't currently expected to run after coalescing--you may get an occasional false assertion.

For register allocators that do lots of live range manipulation and keep live intervals up to date, it may be better to strip the kills and regenerate from the live intervals after allocation. ...maybe a moot point if you're not using live intervals.

-Andy

On Oct 29, 2010, at 6:29 AM, Jeff Kunkel wrote:

> I am wondering about register allocation when there is a kill flag on the MachineOperand. Do I need to remove the kill flag? 
> 
> This code below is just an example from test\CodeGen\X86\xor.ll
> 
> 
> # Machine code for function test3:
> Frame Objects:
>  fi#-2: size=4, align=4, fixed, at location [SP+8]
>  fi#-1: size=4, align=8, fixed, at location [SP+4]
> Function Live Outs: %EAX
> 
> BB#0: derived from LLVM BB %entry
>        %reg16385<def> = MOV32rm <fi#-2>, 1, %reg0, 0, %reg0; mem:LD4[FixedStack-2] GR32:%reg16385
>        %reg16384<def> = MOV32rm <fi#-1>, 1, %reg0, 0, %reg0; mem:LD4[FixedStack-1] GR32:%reg16384
>        %reg16388<def> = MOV32ri 1; GR32:%reg16388
>        %reg16392<def> = XOR32ri %reg16385, 4294967294, %EFLAGS<imp-def>; GR32:%reg16392,16385
>        %reg16391<def> = AND32rr %reg16392<kill>, %reg16384, %EFLAGS<imp-def>; GR32:%reg16391,16392,16384
>        %reg16389<def> = SHR32ri %reg16391, 1, %EFLAGS<imp-def>; GR32:%reg16389,16391
>        %EAX<def> = COPY %reg16389; GR32:%reg16389
>        RET
> 
> After my reg allocation I have 
> 
> # After Register Allocation:
> # Machine code for function test3:
> Frame Objects:
>  fi#-2: size=4, align=4, fixed, at location [SP+8]
>  fi#-1: size=4, align=8, fixed, at location [SP+4]
> Function Live Outs: %EAX
> 
> BB#0: derived from LLVM BB %entry
>        %EAX<def> = MOV32rm <fi#-2>, 1, %reg0, 0, %reg0; mem:LD4[FixedStack-2]
>        %ECX<def> = MOV32rm <fi#-1>, 1, %reg0, 0, %reg0; mem:LD4[FixedStack-1]
>        %EDX<def> = MOV32ri 1
>        %EAX<def> = XOR32ri %EAX, 4294967294, %EFLAGS<imp-def>
>        %EAX<def> = AND32rr %EAX<kill>, %ECX, %EFLAGS<imp-def>
>        %EAX<def> = SHR32ri %EAX, 1, %EFLAGS<imp-def>
>        RET _______________________________________________
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