[LLVMdev] LLVM SSA
martinaide1 at yahoo.com
Sat Sep 26 07:44:00 PDT 2009
I am familiar with the LLVM IR a little bit and I am parsing much more
complex examples. I just gave this example, to show that I would like to
have only 1 variable, not 2, the way SSA would generate it.
I am actually using LLVM purely as a front end to translate to .bc files and
then I have my own parser from there.
At any rate, is there an option to the llvm-gcc --emit-llvm to tell it to
produce .bc files that are at least space optimized (or even better, not in
SSA form) ?
Óscar Fuentes wrote:
> ivtm <martinaide1 at yahoo.com> writes:
>> I am wondering if there are options that can be given to LLVM can be used
>> generate code that is not in SSA, but in plain 3-address form ? (for
>> example, if there is an existing pass that does the register allocation
>> dead variable elimination)
>> For example, if I have:
>> int x = 0;
>> void main()
>> I guess, if that is not the case, then, one needs to write their own
> Why do you want to avoid SSA?
> SSA on LLVM is much simpler than it seems, the API makes generating SSA
> natural, almost not noticing it. Your above example is trivial. Go to
> http://www.llvm.org/demo and see how your C/C++ code is translated to
> LLVM IR (pay attention to the options available on the web form).
> And of course there are passes for register allocation, dead variable
> elimination and more.
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
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