[LLVMdev] MIPS backend and VFPU

[jetcube]

I noticed that the MIPS backend was developed as a backend for the
generic MIPS processor and also as a Google SoC targeting the Allegrex
CPU, however there is no support for vector instructions. I see that
vectorization is a very powerfull weapon from LLVM when compared to
other compilers but in the case of the Allegrex CPU it is not
supported. Are there any plans in the near future to add support for
it?

If not, which CPUs have some kind of VFPU support already implemented
so someone totally noob into the LLVM tablegen could try to look to
add it?