[LLVMdev] DataStructure Analysis ds-aa can not stop when passing mysqld

[hc2428 at columbia.edu]

Quoting hc2428 at columbia.edu:

Dear staff,
     I try to use anders-aa to pass the mysqld.bc3 in my previous  
email, but it does not work.

Command: opt -anders-aa mysqld.bc3 -disable-output

Output:
Unknown instruction:    %mrv4 = insertvalue %struct.ACL_ACCESS undef,  
i64 %mrv, 0               ; <%struct.ACL_ACCESS> [#uses=1]
opt[0x9e886c]
opt[0x9e898e]
/lib/libc.so.6[0x7fb96ab8b100]
/lib/libc.so.6(gsignal+0x35)[0x7fb96ab8b095]
/lib/libc.so.6(abort+0x110)[0x7fb96ab8caf0]
opt[0x875c8a]
opt[0x876149]
opt[0x876169]
opt[0x87a331]
opt[0x87a38f]
opt[0x87a3e4]
opt[0x87a429]
opt[0x87a47e]
opt[0x87a4a3]
opt[0x87a8c8]
opt[0x87ab50]
opt(_ZN4llvm13MPPassManager11runOnModuleERNS_6ModuleE+0xba)[0x977982]
opt(_ZN4llvm15PassManagerImpl3runERNS_6ModuleE+0x74)[0x979296]
opt(_ZN4llvm11PassManager3runERNS_6ModuleE+0x21)[0x9792f9]
opt(main+0xf7e)[0x6c4ae6]
/lib/libc.so.6(__libc_start_main+0xf4)[0x7fb96ab771c4]
opt(cos+0x119)[0x6b5089]
Aborted

> Quoting hc2428 at columbia.edu:
>
> Dear staff,
>     Here is the bc file.
>
> Heming
>
>> Quoting Chris Lattner <clattner at apple.com>:
>>
>> Dear staff,
>>     I am using the ds-aa to pass mysqld. I compile mysqld 4.0.12
>> statically (compile all libraries statically to the executable) and
>> got the bc file, named it as mysqld.bc3.
>>     I use the command to pass:
>>
>> opt -load <poolalloc install dir>/lib/libLLVMDataStructure.so -ds-aa
>> mysqld.bc3 -print-alias-sets -disable-output
>>
>>     However, I got a lot of "cast in ... " on output screen like this:
>>
>> cast in strxnmov
>>         %13 = inttoptr i32 %10 to i8*           ; <i8*> [#uses=1]
>>
>>     In addition, and pass can not stop for a long time, and the last
>> output is the "cast in ... " as above.
>>
>> Thanks,
>> Heming
>>
>>
>>>
>>> On May 13, 2009, at 7:22 AM, Stripf, Timo wrote:
>>>
>>>> Hi all,
>>>>
>>>> i?m working atm on a backend for a processor architecture that is
>>>> capable of storing the carry flag of ADDC in an 1-bit register
>>>> class. So I tried to lower the ADDC instruction to generate two
>>>> register values as result. On the tablegen description of the
>>>> instruction i came across the tablegen restriction that only one
>>>> output result of one instruction is possible:
>>>>
>>>> assert(NumResults <= 1 &&
>>>>        "We only work with nodes with zero or one result so far!");
>>>>
>>>> So my question is now how much work it would be to remove this
>>>> restriction in tablegen. What do I have to take into consideration?
>>>>
>>>
>>> I don't know offhand, but this would be a very welcome improvement!
>>>
>>> -Chris
>>
>>
>>
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>>