[LLVMdev] TableGen: NumResults <= 1 restriction

[Stripf, Timo]

Hi all,

i'm working atm on a backend for a processor architecture that is
capable of storing the carry flag of ADDC in an 1-bit register class. So
I tried to lower the ADDC instruction to generate two register values as
result. On the tablegen description of the instruction i came across the
tablegen restriction that only one output result of one instruction is
possible:

  assert(NumResults <= 1 &&
         "We only work with nodes with zero or one result so far!");

So my question is now how much work it would be to remove this
restriction in tablegen. What do I have to take into consideration?

Thanks,
Timo Stripf