[LLVMdev] RFC: AVX Pattern Specification [LONG]

[Chris Lattner]

On May 5, 2009, at 9:31 AM, David Greene wrote:

> On Tuesday 05 May 2009 01:02, Evan Cheng wrote:
>
>> I think it makes sense for isel to use HW cost (instruction latency,
>> code size) as a late tie breaker. In that case, shouldn't cost be  
>> part
>> of instruction itinerary?
>
> What latency?  Each implementation has its own quirks and LLVM must be
> flexible enough to handle them.  So cost needs to be a function of
> the CPU type as well as the instruction.

For shuffles, I don't have a strong opinion.  I just want dag combiner  
to be able to say "if these two shuffles have greater or equal cost to  
the equivalent combined shuffle, then merge the shuffles into one".   
It doesn't matter what units these are in.  The other use is to break  
ties between multiple instructions that can match the same shuffle  
pattern.  For these, the precise units also don't matter.

Looking further ahead to a world where we have vectorization, we will  
need very precise cost models for various vector operands, scalar  
operations etc.  I don't think it necessarily makes sense to  
overconstraint a solution for shuffles in the short term though.

-Chris