[LLVMdev] A question about backend implementation of instructions with special register allocation needs.

[Anton Korobeynikov]

Hello, Gil

>    double store :   Ri,Ri+1  are stored to the memory at address
> specified by (Rj).
Why don't define new register class for such sort of things with wide
"virtual" registers containing Ri,Ri+1 as subregs? You can emit such
wide stores and even do some post-pass to convert narrow stores into
wide one (look into ARM's multiple store pass). Recently added
regalloc hints will even help regalloc to generate narrow stores which
can be turned into wide later.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University