[LLVMdev] Help: Instruction Pattern Matching question
hisham_chow at yahoo.com
Thu Jul 9 20:09:55 PDT 2009
I am having some trouble matching patterns in targetinstructioninfo.td file with the CodeGen expectation. Could anybody please help?
Here is the example:
I want to emit instruction for adding 2 different kind of oprands. Basically i want to mix register types when I define the instruction for add,sub etc
I define the instruction TargetInstruction.td as follows:
<opcode op,subopcode subop,
dag outs, dag ins, string asmstr,list<dag> pattern>
let Namespce = "MyNameSpace";
MyOpCode myop = op;
MySubOpcode mysubop = subop;
dag OutOprandList = outs;
dag InOprandList = ins;
let ASMString = asmstr;
let Pattern = pattern;
def My_ADDINST1: MyInst <MYADD1, NO_SUBOP,
(outs ptr_rc: $dest), (ins: $ptr_rc:$ptr1, Int32RC:$src)
"myadd1 $dst, $ptr1, $src1",
[(set $ptr_rc:$dst,(add $ptr_rc:ptr1, Int32RC:$src))]>;
it is giving me error like impossible to select.
Could anybody help me resolve this issue. Any example would be highly appreciated.
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