[LLVMdev] Help on DAG pattern matching string

[Bill Wendling]

That's kind of strange. It might be some type of "default". However,  
you probably don't want to turn off the "commutative" property, unless  
it really isn't commutative. I know it's painful, but it might be best  
just to slog through the TableGen code in a debugger, and see why it  
is that your stuff inherits properties from the ADD in  
TargetSelectoinDAG.td and then why the two versions are "identical" in  
TableGen's mind.

-bw

On Jul 5, 2009, at 7:15 PM, Javier Martinez wrote:

> Hi Bill,
>
> Yes, there are other patterns. I tried commenting out all the other  
> instructions definitions and I still get this error. After debugging  
> TblGen I found that the second pattern is being generated as a  
> variant of the first. I think the reason is that the PADD  
> instruction is inheriting the commutative property from ADD defined  
> inTargetSelectionDAG.td. The variant ends up being the same as the  
> original causing the error later on. If all this is correct then how  
> can I mark the node to be non-commutable? I tried using "let  
> isCommutable = 0" in the instruction definition but didn't seem to  
> work.
>
> Thanks,
> Javier
>
>
> On 7/4/2009 3:08 PM, Bill Wendling wrote:
>>
>> Are there any other patterns in your TD file? If so, then one of the
>> ones before this pattern will match everything, and this pattern will
>> never be matched.
>>
>> -bw
>>
>> On Jul 3, 2009, at 8:27 PM, Javier Martinez wrote:
>>
>>
>>> Hello,
>>>
>>> I'm new to LLVM and I'm using it to translate from LLVM to another
>>> language rather than emitting actual machine code. The target  
>>> language
>>> has instructions that operate on pointers which aren't naturally
>>> exposed
>>> in LLVM. Here's what I've done to add pointer support for an
>>> instruction
>>> called PADD that takes a pointers and an offset and returns the new
>>> pointer value:
>>>
>>> def DefReg : Register<"r">;
>>> def PtrReg : Register<"ptr">;
>>> def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>;
>>> def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>;
>>> def BEInst<bits<8> op, dag outs, dag ins, string asmstr, list<dag>
>>> pattern> : Instruction { /* assign arguments to class members */ }
>>> def BE_PADD : BEInst<0F, (outs P32RC:$dst), (ins P32RC:$src1,
>>> I32RC:$src2), "PADD",
>>>                                       [(set P32RC:$dst, (add
>>> P32RC:$src1, I32RC:$src2))]>;
>>>
>>> When I compile the project I get the error: Pattern '(add:i32
>>> P32RC:i32:$src1, I32RC:i32:$src2)' is impossible to select! Does
>>> anyone
>>> have an idea of why I'm getting this error?
>>>
>>> I've read the docs on table generator, code generator, back end,  
>>> etc.
>>> but I'm still unclear on how to write pattern selection strings.  
>>> Area
>>> there resources other than the LLVM docs that explain this more in
>>> detail?
>>>
>>> Thanks,
>>> Javier
>>> _______________________________________________
>>> LLVM Developers mailing list
>>> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>>
>>
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