[LLVMdev] Possible bug in LiveIntervals (triggered on the XCore target)?

[Richard Osborne]

Evan Cheng wrote:
> On Jan 13, 2009, at 11:20 AM, Richard Osborne <richard at xmos.com> wrote:
>
>   
>> Roman Levenstein wrote:
>>     
>>> Hi again,
>>>
>>> Now, after I fixed the graph coloring regalloc bug that was triggered
>>> by the ARM target, I continue testing and found another bug, this  
>>> time
>>> on the XCore target. First I thought that it is again specific to my
>>> register allocator, but it seems to be trigerred also by LLVM's
>>> linearscan register allocator.
>>>
>>> I don't know if the XCore target is stable enough in LLVM, or may  
>>> be I
>>> should just safely skip it during testing because it is not mature
>>> yet. Anyway, I report it here - may be it is of some interest.
>>>
>>> The crash happens in LiveIntervalsAnalysis, inside the spilling
>>> function. From what I observe, I'd say it is related to
>>> rematerializable intervals.
>>>
>>> The assertion says:
>>> /opt/llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:142:
>>> llvm::LiveInterval& llvm::LiveIntervals::getInterval(unsigned int):
>>> Assertion `I != r2iMap_.end() && "Interval does not exist for
>>> register"' failed.
>>>
>>> I attach the BC file generated by bugpoint, so that you can  
>>> reproduce it.
>>>
>>> The command-line I use is:
>>> llc --regalloc=linearscan --march=xcore  -f bugpoint-reduced- 
>>> simplified.bc
>>>
>>> Any ideas about the reasons of this bug?
>>>
>>> Thanks,
>>>  -Roman
>>>       
>> It looks like it is trying to rematerialize a load from fixed stack  
>> slot (LDWSP instruction). This has an implicit use of the SP  
>> register which is non allocatable.
>>
>> rewriteInstructionsForSpills calls getReMatImplicitUse which returns  
>> the SP register. This is then followed by a call to getInterval for  
>> this register which fails. The attached patch causes  
>> getReMatImplicitUse to ignore non allocatable physical registers,  
>> which fixes the issue for me. Does this look OK?
>>     
>
> This patch assumes non allocatable registers are available at any  
> point. I don't think that's a safe. Can you change LDWSP so it doesn't  
> implicitly use sp? Once the frame index object is lowered by PEI, it  
> can be rewritten to explicitly use sp. Would that work?
>
> Evan
OK, that make sense, I'll take a look at changing this. I've added a bug 
for the issue:

http://llvm.org/bugs/show_bug.cgi?id=3324

There is currently no Backend: XCore component in bugzilla so I've put 
it under new-bugs. Could someone add this component for me.

Thanks

-- 
Richard Osborne | XMOS
http://www.xmos.com