[LLVMdev] Possible bug in the ARM backend?

[Evan Cheng]

On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote:

> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1:
>    Predecessors according to CFG: 0x8fdac90 (#0)
>        %R0<def> = MOVi 0, 14, %reg0, %reg0
> ***     STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4)
> [0x8fc2d68 + 0]
>        %LR<def> = LDR <fi#0>, %reg0, 0, 14, %reg0
>        %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg0
>        BX_RET 14, %reg0

Ok, ignore my earlier email about BX_RET. The issue is LR should be  
added to livein of BB #1.

**** Post Machine Instrs ****
# Machine code for Insert():
Live Ins: R0 in VR#1025  R1 in VR#1026

entry: 0x8fdac90, LLVM BB @0x8fc2c48, ID#0:
Live Ins: %R0 %R1
        %LR<def> = MOVr %R0, 14, %reg0, %reg0
        CMPri %R0<kill>, 0, 14, %reg0, %CPSR<imp-def>
        Bcc mbb<UnifiedReturnBlock,0x8fdad70>, 10, %CPSR<kill>
    Successors according to CFG: 0x8fdad00 (#1) 0x8fdad70 (#2)

bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1:
    Predecessors according to CFG: 0x8fdac90 (#0)
        %R0<def> = MOVi 0, 14, %reg0, %reg0
        STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4)
[0x8fc2d68 + 0]
        BX_RET 14, %reg0

Here the STR is using LR, but there isn't a def earlier.

Evan