[LLVMdev] A partial reply to the previous question and another one

[Richard Pennington]

Gil Dogon wrote:
[snip]
> Also I will need to introduce new intrinsics specific to our processor, 
> as an example to get me started I would
> like to ask the forum (as recommended in the 'extending llvm' document) 
> how to extend it to support the following:
> (or maybe there is already some support ...)
> 
> double load (load Ri, Ri+1 from an immediate address).
> double store  (store Ri,Ri+1 to an immediate address).
> 
> actually double load is specially challenging as an intrinsic syntax you 
> would have to return two values ....

If you are trying to support e.g. 64 bit data on a processor
with only 32 bit operations, LLVM does all the work for you.

Define the 32 bit insructions in your code generator and LLVM aill 
automagically use them for 64 bit operations.

-Rich