[LLVMdev] Possible error in LegalizeDAG

[Villmow, Micah]

> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
On
> Behalf Of Eli Friedman
> Sent: Thursday, February 19, 2009 11:18 AM
> To: LLVM Developers Mailing List
> Subject: Re: [LLVMdev] Possible error in LegalizeDAG
> 
> On Thu, Feb 19, 2009 at 10:35 AM, Villmow, Micah
<Micah.Villmow at amd.com>
> wrote:
> > On the hardware that I am targeting, which is not a CPU, I must
support
> > i8 loads, however the hardware only supports natively 32bit aligned
> > loads, therefore I have to read in 4 i8's and unpack them and shift
them
> > based on the read address.  So any i8 load has a 75% chance of being
> > unaligned on my hardware,
> 
> Oh, okay, makes sense.
> 
> > I've tried setting setLoadXAction to Custom, Legal, Expand and
Promote.
> > Setting it to Expand does not expand it to
> > sign_extend and load but to  extload and sign_extend, but I don't
> > support extload either.
> 
> I suppose you could consider that a bug.  That said, why is this
> difficult to implement?  You can just treat an extload of an i8 as a
> load of an i8 and get correct code, no?
> 
[Micah Villmow] The problem with the extload is that it is still
generating a 32bit extload instead of an 8bit extload.
> -Eli
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