[LLVMdev] help: about how to use tblgen to constraint operand.

[任坤]

I define a pattern to move two 32bits gpr to 64bits fpr. like arm instructure fmdrr.
But I need to use an even/odd register pair to save  its 2 operands.
I define in mytarget.td:

myfmdrr:
 SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
     SDTCisSameAs<1, 2>]>;
def my_fmdrr : ...........
def myFMDRR : ....
                      (outs FPR: $result), ins(GPR: $op1, GPR:$op2 )
                       [(setFPR: $result, (my_fmdrr GPR: $op1, GPR:$op2) )]

I create myfmdrr instructure in mytargetISelLowering.cpp. and its operands are in R0 and R1.
But after optimization, the operands are save R2 and R1. I know optimization pass does not 
know myfmdrr operands constraint. But How I tell optimzition pass by tblgen??

Could I can control operand constraint in mytargetiSelLowering.cpp? How do I control?? 




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