[LLVMdev] Prevent node from being combined

[Alex]

How can  I prevent some nodes from being combined in DAGCombine.cpp?

Maybe what I want to do below doesn't follow the philosophy of LLVM, but I'd
like to know if there is any way to avoid node from being combined.
TargetLowering::PerformDAGCombine() is only called if DAGCombiner cannot
combine a specific node. It seems that there is no chance to stop it from
combining a node.

I need the shuffle mask in the machine instruction but sometimes if a
vector_shuffle can only return LHS or RHS, it's removed/combined so that I
cannot match vector_shuffle in the instruction selector.

If the vector_shuffle is combined, I have to write the instruction selector
like these:

def SUBvv: MyInst<(ins REG:$src0, imm:$mask0, REG:$src1, imm:$mask1),
           [sub (vector_shuffle REG:$src0, REG:$src0, imm:$mask0),
           (vector_shuffle REG:$src1, REG:$src1, imm:$mask1)]

def SUBrv: MyInst<(ins REG:$src0, REG:$src1, imm:$mask1),
           [sub REG:$src0,
                (vector_shuffle REG:$src1, REG:$src1, imm:$mask1)]

def SUBvr: MyInst<(ins REG:$src0, imm:$mask0, REG:$src1),
           [sub (vector_shuffle REG:$src0, REG:$src0, imm:$mask0),
                REG:$src1)]

Otherwise, I can write:

def SUB: MyInst<(ins REG:$src0, imm:$mask0, REG:$src1, imm:$mask1),
           [sub (vector_shuffle REG:$src0, REG:$src0, imm:$mask0),
           (vector_shuffle REG:$src1, REG:$src1, imm:$mask1)]

And processing MachineInstr will be easier since the operand index of
writemask is always the same for all instructions.
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