[LLVMdev] Multiclass patterns

[Villmow, Micah]

Bill,
 Thanks for the tip, but is not what I am looking to do. From my
understanding of multiclass is that it creates multiple instructions
derived from the Instruction class, which goes in the direction of
multiple target-independent nodes into a single target-dependent node.
However, what I want is something similar but derived from the Pattern
class. This has the opposite affect of taking a single
target-independent node and producing multiple target-dependent nodes. 
I could use the standard multiclass, but it has been stated on this list
that it is not advised to generate multiple instructions via the text
expansion but to use patterns instead.

Sorry for the confusion.

Micah

-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
On Behalf Of Bill Wendling
Sent: Tuesday, February 10, 2009 11:17 AM
To: LLVM Developers Mailing List
Subject: Re: [LLVMdev] Multiclass patterns

On Tue, Feb 10, 2009 at 8:27 AM, Villmow, Micah <Micah.Villmow at amd.com>
wrote:
> Bill,
>  Sorry if I wasn't clear enough. I wasn't referring to multiclass's
that
> define other classes, but with using patterns inside of a multiclass
to
> reduce redundant code.
> For example:
> multiclass IntSubtract<SDNode node>
> {
>    def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1),
>               (ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>;
>    def _i32 : Pat<(sub GPRI32:$src0, GPRI32:$src1),
>               (ADD_i32 GPRI32:$src0, (NEGATE_i32 GPRI32:$src1))>;
> }
>
> or something similar.
> I just want to write the pattern once and then have it apply to
multiple
> register types, i.e. a generic pattern rule for many different
register
> classes.
>
Please look at the documentation for "multiclass" and "defm". In the
X86InstrSSE.td file, we have this, which looks very similar to what
you have above.

let Constraints = "$src1 = $dst" in {
multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
                                  SDNode OpNode, Intrinsic F32Int,
                                  bit Commutable = 0> {
  // Scalar operation, reg+reg.
  def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1,
FR32:$src2),
                 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
                 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
    let isCommutable = Commutable;
  }

  // Scalar operation, reg+mem.
  def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
                                 (ins FR32:$src1, f32mem:$src2),
                 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
                 [(set FR32:$dst, (OpNode FR32:$src1, (load
addr:$src2)))]>;

  // etc.
}
}

// Arithmetic instructions
defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss,
1>;

-bw
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